1. Field of Invention
The present invention relates to an electronic circuit device. More particularly, the present invention relates to a clock gate buffering circuit that includes a functional circuit without a latch, that receives a clock signal and an enable signal, and outputs a clock gate signal.
2. Description of Related Art
Clock gate device is an important device and is often used in a digital circuit, especially the low voltage circuits, for example. A conventional clock gate device has many disadvantages, such as an output of an enable signal is unstable when a glitch occurs, and a time skew further occurs.
FIG. 1 illustrates a conventional circuit of the clock gate. The circuit includes a AND gate that receives a clock signal CK and an enable signal E, and sends a clock gate signal GCK. A performance logic table is shown below:
wherein X represents at any state signal. There are some disadvantages in the circuit of the clock gate in FIG. 1. The major disadvantage is a signal glitch of the enable signal that makes a noise when the clock signal CK is 1. The noise will send to the clock gate signal and effect the state of flip-flop (FF) device in next level and make an error.
Another conventional circuit has been developed to solve the problem of the signal glitch. FIG. 2 illustrates another conventional circuit of the clock gate. In FIG. 2, the circuit further includes a latch to control the clock signal. The performance logic table is shown below:
The circuit of the clock gate circuit is normally designed for a dynamic clock gate signal in FIG. 2. According to this design, the glitch signal of the enable signal cannot send a signal to the functional circuit element in next level. However, a latch is the major disadvantage in the circuit. The setup time and the transition time between the enable signal and the clock signal need to calculate. The clock skew is very easy occurred.
The invention provides a clock gate circuit. As embodied and broadly described herein, the invention provides a functional circuit without a latch. More particularly, the functional circuit of this invention receives a clock signal and an enable signal. When the clock rate is rising, the functional circuit sends a clock gate signal according to a logical voltage level of the enable signal. And when the clock rate is falling, the functional circuit also sends a clock gate signal.
The circuit of clock gate is a functional circuit without the latch. There are several advantages in this invention, including simplifying the circuit, reducing the size of circuit, reducing the consumption of power, reducing the transition time between the clock signal and the clock gate signal, reducing the clock skew, reducing the setup time between the enable signal and the clock signal, and simplifying the management of the power.
In above describing, a logical state of the clock gate signal and the enable signal is either consistent of or opposite to each other. More particularly, the enable signal is either a logical high or a logical low signal.
The functional circuit includes a first inverter, a first functional gate circuit and a NOR gate. The first inverter receives a clock signal and sends a first signal. The first functional gate circuit receives an enable signal and the first signal, and sends a second signal. The NOR gate receives the second signal and the clock signal and sends a clock gate signal.
Instead, the functional circuit includes a first inverter, a first functional gate circuit and an AND gate. The first inverter receives a clock signal and sends a first signal. The first functional gate circuit receives an enable signal and the first signal, and sends a second signal. The AND gate receives the second signal and the clock signal, and sends a clock gate signal.
In addition, this invention also provides a clock gate buffering circuit, including a functional circuit without a latch. The functional circuit of the clock gate buffering circuit receives a clock signal and an enable signal. When the clock signal is a falling, a logical voltage level of the enable signal sends a clock gate signal. When the clock is a rising, the functional circuit of the invention always sends a clock gate signal of logical high.
In above describing, the functional circuit receives a logical state of the clock gate signal and the enable signal either consistent of or opposite to each other when the clock is falling. More particularly, the enable signal is either a logical high or a logical low signal.
The functional circuit of the invention includes a first functional gate circuit and an OR gate. The first functional gate circuit receives an enable signal and a clock signal, and sends a first signal. The OR gate receives the first signal and the clock signal, and sends a clock gate signal.
Instead, the functional circuit includes a first functional gate circuit, a first inverter and a NAND gate. The first functional gate circuit receives an enable signal and a clock signal, and sends a first signal. The first inverter receives the clock signal and sends a second signal. The NAND gate receives the first and second signals and sends a clock gate signal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.